1. Field of the Invention
The present invention relates in general to systems for generating a timing signal and in particular to a timing system employing a retriggered voltage controlled oscillator for reducing jitter.
2. Description of Related Art
The present invention relates to a timing signal generator useful, for example, for synchronizing in an integrated circuit (IC) tester. An IC chip typically has pads on its surface providing access points for its input and output signals. The IC's pins are connected to these pads when the chip is packaged. However before the integrated circuit (IC) is packaged it can be tested by an integrated circuit tester having a set of probes for contacting the IC's pads. To test an IC the tester transmits input signals to various nodes of the device under test (DUT) and samples various output signals produced at nodes of the DUT in response to the input signals. In a distributed tester architecture, the tester employs a separate "node processor" for each test node of the DUT. Each node processor is a separate integrated circuit and handles signal transmission and sampling for its node. Since the timing of input signal transmission and output signal sampling is critical, a clock signal is sent in common to each node processor and each node processor includes a timing signal generator for controlling the timing of signal transmission and sampling using the clock signal as a timing reference.
U.S. Pat. No. 4,902,986 issued Feb. 20, 1990 to Gary Lesmeister describes a prior art timing signal generator similar to that illustrated herein at FIG. 1. Timing signal generator 10 generates a TIMING signal 12 having pulses occurring at desired times relative to assertion of a START signal 14. Timing circuit 10 includes a free-running ring oscillator 16 consisting of a set of N identical inverter stages S1 through SN connected in series to form a ring. Each inverter stage S1-SN has a similar signal propagation delay D. When N is an odd number, the taps TA(1)-TA(N) at the nodes between the inverter inputs and outputs oscillate with a period that is 2.times.N.times.D at 50% duty cycle. Although the tap signals TA(1)-TA(N) are all of the same frequency they are shifted in phase one from another by 2.times.D, or twice the stage propagation delay. The leading edges of pulses of tap signals TA(1)-TA(N) are thus evenly distributed in time and serve to divide the oscillator period of 2.times.N.times.D into N equal time slots.
Since the propagation delay D of inverters S1-SN is a function of the power supply voltage VPLL supplied in common to all the inverters S1-SN, the frequency of signals T1-TN (1.backslash.2ND) can be controlled by adjusting the voltage of VPLL. A reference oscillator 18 produces an output clock signal (CLOCK) supplied as input to a phase lock controller 20. A delay circuit 22 delays tap signal T1 to provide a second input T1X to phase lock controller 20. Controller 20 includes a phase detector 20A comprising CLOCK to T1X and driving a charge pump 20B charging a capacitor 20C to produce the VPLL signal controlling the frequency of tap signals T1-TN. When CLOCK leads T1X, controller 20 increases the voltage of VPLL to increase the frequency of tap signals TA(1)-TA(N). When CLOCK lags T1X, controller 20 decreases the voltage of VPLL to decrease tap T1-TN signal frequency. Thus controller 20 phase locks signal T1X to CLOCK. Since T1X is derived from T1, all tap signals TA(1)-TA(N) are frequency locked to CLOCK.
The timing signal generator 10 includes a multiplexer 24 for selecting any one of the tap signals TA(1)-TA(N) as the TIMING signal output. A logic circuit 28 clocked by the CLOCK signal receives an externally generated START signal 14 and controls the tap signal selection made by multiplexer 24 in a manner indicated by input programming data (DATA) supplied to logic circuit 28. Logic circuit 28 may be programmed to switch multiplexer 24 "on-the-fly" so that multiplexer 24 changes its tap signal selection from time to time according to a predetermined pattern. Depending on the switching pattern of multiplexer 24, the TIMING signal may provide one or more pulses at a predetermined times after START signal 14 is asserted. The TIMING signal pulses may be periodic with a frequency that differs from that of the CLOCK signal or may be irregularly spaced.
The delay provided by delay circuit 22 is set equal to the propagation delay of the selected tap signal through multiplexer 24 so that TIMING signal pulses will have predictable phase relationships with CLOCK signal pulses. For example, if multiplexer 24 always selects tap T1, then the TIMING signal will have the same phase as signal T1X at the input of phase lock controller 20. Since T1X is phase locked to CLOCK, TIMING signal pulses will also be phase locked to the CLOCK signal. If multiplexer 24 selects any other tap signal T2-TN, the TIMING signal pulses will be phase shifted from CLOCK signal pulses by a known amount, the phase difference between T1 and the selected tap signal.
Although oscillator 16 is frequency locked to the stable CLOCK signal, the CLOCK signal is only loosely coupled to the oscillator output signal T1 through phase controller 20. The delay inherent in the feedback loop limits the ability of the feedback loop to quickly dampen oscillations in the phase of the tap signals T1-TN in response to system noise. Such oscillation ("jitter") in tap signal phase limits the timing resolution that may be achieved. Although we can increase the number N of stages in the ring to improve timing resolution, at some point signal jitter overwhelms the nominal phase differences between adjacent taps and further increases in N provide no increase in timing resolution. Also any variation between the delay provided by delay circuit 22 from the delay provided by multiplexer 24 can cause an error in the timing of pulses of the TIMING signal. Such variation can result from temperature or IC process variations between the devices forming circuit 22 and those forming multiplexer 24.
What is needed is a timing signal generator for producing a highly stable timing signal having pulses of adjustable timing relative to pulses of a stable reference clock.